Chip Gallery

Chip Gallery 2018-05-20T18:27:23+00:00
  • Chip Description:
    World’s first CMOS passive magnetic-free non-reciprocal circulator based on staggered commutation
  • Technology:
    65nm CMOS
  • Date:
    May 2015
  • Chip Description:
    Receiver with Integrated Magnetic-Free N-Path-Filter-Based Non-Reciprocal Circulator and Baseband Self-Interference Cancellation for Full-Duplex Wireless
  • Technology:
    65nm CMOS
  • Date:
    May 2015
  • Chip Description:
    Scalable Spatio-Spectral-Filtering 4-Element MIMO Receiver Array with Spatial Notch Suppression Enabling Digital Beamforming
  • Technology:
    65nm CMOS
  • Date:
    May 2015
  • Chip Description:
    6th Order All-Passive N-Path Filter
  • Technology:
    65nm CMOS
  • Date:
    October 2014
  • Chip Description:
    Reconfigurable Receiver with >20MHz Bandwidth RF Self-Interference Cancellation Suitable for FDD, Co-existence and Full-Duplex Applications
  • Technology:
    65nm CMOS
  • Date:
    May 2014
  • Chip Description:
    World’s First 60GHz CMOS Transceiver Front-End for Same-Channel Full-Duplex Wireless Communication
  • Technology:
    45nm CMOS SOI
  • Date:
    February 2014
  • Chip Description:
    0.6GHz-9GHz RF Channelizer using Iterative Down-Conversion
  • Technology:
    65nm CMOS
  • Date:
    May 2013
  • Chip Description:
    Blocker-Resilient Wideband Receiver with Low-Noise TX-Leakage Cancellation for FDD/Co-existence
  • Technology:
    65nm CMOS
  • Date:
    May 2013
  • Chip Description:
    RF power DAC with Integrated FIR Filtering
  • Technology:
    65nm CMOS
  • Date:
    May 2013
  • Chip Description:
    4-5.84 GHz RF Instantaneous-Hop Frequency Synthesizer
  • Technology:
    65nm CMOS
  • Date:
    May 2013
  • Chip Description:
    200 GHz power mixer with device nonlinearity engineering to improve output harmonic content
  • Technology:
    130nm CMOS
  • Date:
    November 2012
  • Chip Description:
    Frequency Doubler with +4dBm Output Power at fmax (134 GHz)
  • Technology:
    130nm CMOS
  • Date:
    November 2012
  • Chip Description:
    42.5GHz Digitally-Controlled Quarter-Wave Load-Modulated Switching PA Array
  • Technology:
    45nm CMOS SOI
  • Date:
    March 2012
  • Chip Description:
    1-bit mmWave 47GHz Class-E-like Power DAC
  • Technology:
    45nm CMOS SOI
  • Date:
    March 2012
  • Chip Description:
    5GHz Area-Efficient Stacked Class-E PA with Transformer-Based Charging Acceleration
  • Technology:
    65nm CMOS
  • Date:
    September 2011
  • Chip Description:
    8-way Power-Combined 33GHz-46GHz Class-E-like PA Array with World Record 27dBm Output Power
  • Technology:
    45nm CMOS SOI
  • Date:
    August 2011
  • Chip Description:
    Q-band 18dBm 2-stacked Class-E-like PA with Record 34% PAE & 20dBm 4-stacked Class-E-like PA
  • Technology:
    45nm CMOS SOI
  • Date:
    August 2011
  • Chip Description:
    17dBm Dual Output Stacked Class-E PA Unit Cell & 2-way Current-combined Dual Output Stacked Class-E PA for Q-band Applications
  • Technology:
    45nm CMOS SOI
  • Date:
    February 2011
  • Chip Description:
    220GHz & 320GHz Maximum-Gain Ring Oscillators
  • Technology:
    45nm CMOS SOI
  • Date:
    July 2010