Simplified Surface Potential Model for 65nm CMOS
Verilog-A code for a Simplified Surface Potential (SSP) model for a 65nm transistor in the triode region for simulations of switch-based circuits
RFIC 2017 slides that explain the SSP model
Typical foundries do not offer all-region models that enable accurate linearity (IIP3) simulations of switch-based circuits, such as passive mixers, mixer-first receivers, N-path filters etc. We have developed a Simplified Surface Potential (SSP) model for 65nm that uses Verilog-A code in conjunction with the foundry-provided models to accurate model the I-V characteristics around 0 drain-source bias, as well as second-order parasitics, such as capacitance and gate leakage current. Please refer to the attached slide deck to understand how to use the model. If you use the model, please reference the paper below in any ensuing publications:
M. B. Dastjerdi and H. Krishnaswamy, “A simplified CMOS FET model using surface potential equations for inter-modulation simulations of passive-mixer-like circuits,” 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, USA, 2017, pp. 132-135.
doi: 10.1109/RFIC.2017.7969035 (link)